1- Supports PCIe 2.0 & 3.0 for AMD FPGAs
2- Tested over 7-Series and Ultrascale & Ultrascale+ series
3- 64-bit source, destination, and descriptor addresses
4- Up to four host-to-card (H2C/Read) data channels
5- Up to four card-to-host (H2C/Read) data channels
6- Selectable user interface
a. Single AXI4 memory mapped (MM) user interface
b. AXI4-Stream user interface (each channel has its own AXI4-Stream interface)
7- AXI4 Master and AXI4-Lite Master optional interfaces allow for PCIe traffic to bypass the DMA engine
8- AXI4-Lite Slave to access DMA status registers
9- Scatter Gather descriptor list supporting unlimited list size
10- 256 MB max transfer size per descriptor